Forum Topic

30. abril 2008 12:39:47

I am conducting a preliminary SIL capability assessment of a product during quotation stage. One of the important aspects to consider is the concept of architectural constraints. I am using table 3 IEC 61508-2 part 2 which gives you a limit of the maxium SIL that can be claimed in terms of SFF and HFT. Now my question is this : at an early stage of the project how can you jugde the HFT of your system without doing an in depth analysis e.g. FMEDA ? As far as I understood in deciding the HFT level, diagnostics cannot be accounted for. So HFT is pure hardware redundancy.

05. mayo 2008 09:00:37

You are right, HFT is a measure of redundancy. Redundancy can be done on architecture level or on device level. When on device level it means that inside the device there is redundancy.

If you have 1oo2 transmitters then you need to determine the SFF with an FMEDA on each transmitter.

If you have a transmitter with internal redundancy, e.g., 1oo2, then you need to perform an FMEDA on each leg/path of this transmitter.

In other words you do it the other way around. First you determine the SFF of each leg/path and then you determine whether you have redundancy or not. If you have redundancy (internal or external) you can then apply the architectural constraints table to see which SIL you achieved for the hardware.